The present invention relates in general to digital clock generating systems, and more particularly to a circuit that will accept as an input a periodic signal of frequency F and produce as an output, two periodic signals of frequency 0.4*F (F/2.5) and 0.2*F (F/5).
It is well known to those skilled in the art that synchronous systems are more stable than asynchronous systems. However, one disadvantage to synchronous systems is their requirement for a master clock with multiple clocks derived from this master source. Problems arise when the master clock must be divided by an inconvenient value, such as 2.5.
Prior to the present invention, the divide by 2.5 would have been done with a Phase Locked Loop (PLL). When a PLL is configured for frequency synthesis, it has as a minimum a Voltage Controlled Oscillator (VCO), phase detector, low pass filter, and a divide by N feedback circuit. Depending on such factors as frequency of operation, stability required and cost, several additional components could be added to the basic frequency synthesis PLL.
In generating the divide by 2.5 function, the frequency synthesis PLL requires a VCO with a center frequency of two times that of the original frequency (F). This makes the VCO a very complex and expensive component when trying to perform a divide by 2.5 function on high frequency clocks. Because the VCO is a function of the original frequency (F), the frequency synthesis PLL and VCO must be redesigned for each frequency that is to be divided.
An additional disadvantage with PLLs is their inherent production of jitter and wonder even when properly designed. Under certain conditions the PLL can become unstable and actually produce a frequency other then the desired one.
Accordingly, it is an objective of the present invention to provide a divide by 2.5 circuit which does not require frequent redesign or a need for expensive components.